Publications
1983. Trade-offs between depth and width in parallel computation. Foundations of Computer Science, 1983., 24th Annual Symposium on. :146-153.
1993. A case for the PRAM as a standard programmer's model. Parallel Architectures and their Efficient Use. :11-19.
2009. Optical interconnect structure in a computer system and method of transporting data between processing elements and memory through the optical interconnect structure. 10/529,310(7505822)
2000. Experiments with list ranking for explicit multi-threaded (XMT) instruction parallelism. J. Exp. Algorithmics. 5
2007. Plasmonics and the parallel programming problem. Society of Photo-Optical Instrumentation Engineers (SPIE) Conference Series. 6477:19-19.
1984. Randomized speed-ups in parallel computation. Proceedings of the sixteenth annual ACM symposium on Theory of computing. :230-239.
1988. PRAM algorithms: teach and preach. collection of position papers, IBM-NSF Workshop on$\textbackslashbackslash$ Opportunities and Constraints of Parallel Computing", IBM Almaden.
1993. Advanced parallel prefix-sums, list ranking and connectivity. Synthesis of Parallel Algorithms. :215-257.
2009. Spawn-join instruction set architecture for providing explicit multithreading. 10/236,934(7523293)
1995. On a Technique for Parsing a String (Invited Lecture). Lecture Notes in Computer Science. 937:386-386.
2007. Models for advancing PRAM and other algorithms into parallel programs for a PRAM-On-Chip platform. IN HANDBOOK OF PARALLEL COMPUTING: MODELS, ALGORITHMS AND APPLICATIONS, EDITORS.
2006. Models for Advancing PRAM and Other Algorithms into Parallel Programs for a PRAM-On-Chip Platform. Technical Reports from UMIACS, UMIACS-UMIACS-TR-2006-21.
1987. Randomized parallel speedups for list ranking* 1. Journal of Parallel and Distributed Computing. 4(3):319-333.
2004. Bending light for multi-chip virtual PRAMs? Proc. 3rd Workshop on Non-Slicon Computation, held in conjunction with the 31st International Symposium on Computer Architecture (ISCA 2004). :19-23.
1997. From algorithm parallelism to instruction-level parallelism: An encode-decode chain using prefix-sum. Proceedings of the ninth annual ACM symposium on Parallel algorithms and architectures. :260-271.