Publications
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[ Author] Title Type Year Filters: First Letter Of Last Name is V [Clear All Filters]
2004. Bending light for multi-chip virtual PRAMs? Proc. 3rd Workshop on Non-Slicon Computation, held in conjunction with the 31st International Symposium on Computer Architecture (ISCA 2004). :19-23.
1984. Randomized speed-ups in parallel computation. Proceedings of the sixteenth annual ACM symposium on Theory of computing. :230-239.
2007. Thinking in parallel: Some basic data-parallel algorithms and techniques. UMIACS, University of Maryland, College Park. 1993
2000. A no-busy-wait balanced tree parallel algorithmic paradigm. Proceedings of the twelfth annual ACM symposium on Parallel algorithms and architectures. :147-155.
1992. A parallel blocking flow algorithm for acyclic networks. Journal of Algorithms. 13(3):489-501.
1987. Randomized parallel speedups for list ranking* 1. Journal of Parallel and Distributed Computing. 4(3):319-333.
2008. An Immediate Concurrent Execution (ICE) Abstraction Proposal for Many-Cores. Computer Science Research Works.
1983. Implementation of simultaneous memory address access in models that forbid it. Journal of algorithms. 4(1):45-50.
2004. PRAM-On-Chip: A Quest for Not-So-Obvious Non-obviousness. Mathematical Foundations of Computer Science 2004Mathematical Foundations of Computer Science 2004. 3153:104-105.
1996. Can parallel algorithms enhance serial implementation? Communications of the ACM. 39(9):88-91.
1991. Can parallel algorithms enhance serial implementation? Parallel Processing Symposium, 1994. Proceedings., Eighth International. :376-385.
2007. Towards Realizing a PRAM-On-Chip Vision. Workshop on Highly Parallel Processing on a Chip (HPPC). 28
2000. Experiments with list ranking for explicit multi-threaded (XMT) instruction parallelism. J. Exp. Algorithmics. 5
1993. A case for the PRAM as a standard programmer's model. Parallel Architectures and their Efficient Use. :11-19.
2009. Optical interconnect structure in a computer system and method of transporting data between processing elements and memory through the optical interconnect structure. 10/529,310(7505822)
1997. From algorithm parallelism to instruction-level parallelism: An encode-decode chain using prefix-sum. Proceedings of the ninth annual ACM symposium on Parallel algorithms and architectures. :260-271.